A problem of crosstalk is pointed out as a specific problem in a TFT-LCD. The crosstalk occurs because adjacent pixels are connected via a parasitic capacitance. In other words, when an insulating film intervenes between a transparent electrode and a source line, a parasitic capacitance is produced between the transparent electrode and the source line. In the same manner, parasitic capacitances are produced between a gate line and the transparent electrode and between the source line and a common electrode, respectively. Due to influence of these parasitic capacitances and a capacitance of a liquid crystal itself, an electric potential of a display pixel becomes different from a desired voltage when a gate is turned OFF. Consequently, a display gradation becomes different from a desired gradation.
In other words, at the moment a gate is high, a desired voltage is applied to a display pixel that is connected to a TFT. However, when the gate is low, the pixel is connected to many peripheral electric circuits via parasitic capacitances. Because many of these peripheral electric circuits are related to panel design, a driving voltage can be set in advance in consideration of parasitic capacitances between the display pixel and the peripheral electric circuits. Therefore, the crosstalk caused by the parasitic capacitances that are formed between the display pixel and the peripheral electric circuits can be compensated in advance. However, an electric potential of a source line that drives other display pixel cannot be determined in advance. Therefore, it is difficult to compensate, in advance, crosstalk that is caused by other source line.
As illustrated in FIG. 6(a), in a liquid crystal display apparatus, source lines Si (“i” is an integer) and gate lines Gj (j is an integer) are provided to be orthogonal. At each intersection of source lines Si and gate lines Gj, a display pixel 100 and a switching element 200 are provided. Regarding a display pixel (A) among the display pixels 100, parasitic capacitances Csda, Csdb, Cgd, and Ccs are formed as follows. A display pixel (B) indicates a display pixel that is adjacent to the display pixel (A) in a direction along which a gate line is provided.
The details of the parasitic capacitances Csda, Csdb, Cgd, and Ccs are as follows:
the parasitic capacitance Csda: a parasitic capacitance that is formed between a source line S2 for driving display pixels (A) and the display pixel (A);
the parasitic capacitance Csdb: a parasitic capacitance that is formed between a source line S3 for driving display pixels (B) and the display pixel (A);
the parasitic capacitance Cgd: a parasitic capacitance that is formed between a gate line G2 for driving display pixels (A) and the display pixel (A); and
the parasitic capacitance Ccs: a parasitic capacitance that is formed between a common electrode line and the display pixel (A).
A capacitance of the display pixel (A) itself is Cp and a voltage which is applied to each gate line varies as shown in FIG. 6(b). Furthermore, while the display pixel (A) displays a G color, the display pixel (B) displays an R color or B color. In addition, in a case where a gradation of the display pixel (A) is LA and a gradation of the display pixel (B) is LB, LA≠LB.
In this case, at the time at which the gate is high, when a drain voltage +V(A) is applied to a liquid crystal part of the display pixel (A), a drain voltage −V (B) is applied to a liquid crystal part of the display pixel (B). Then, when a next gate line is turned ON, −V (A) is applied to the source line that drives the display pixel (A) and +V (B) is applied to a source line that drives the display pixel (B).
However, in the reality, the above-mentioned drain voltage is not applied directly to the display pixel (A). A drain voltage that is varied due to the influence of the parasitic capacitances is applied to the display pixel (A). Specifically, an effective value Va of a voltage that is applied to the display pixel (A) is represented byVa=V(A)+(Csda*V(A)+Cgd*Vg+Csdb*V(B)+Ccs*Vc)/Cp, 
where: Vg is a voltage that is applied to the gate line; and Vc is a voltage that is applied to an opposed electrode.
In this way, a voltage different from a desired drain voltage (A) is applied to the display pixel (A).
The parasitic capacitances Csda, Cgd, and Ccs that are formed between the display pixel (A) and the respective lines as mentioned above are predictable at a stage of designing. Therefore, a drain voltage can be set in consideration of values of the parasitic capacitances. Accordingly, these parasitic capacitances do not have much influence on a display gradation of the display pixel (A).
However, the calculation formula of the effective voltage Va above includes the parasitic capacitance Csdb and a drain voltage V(B). In other words, the voltage Va is influenced by the source line that is connected to the display pixel (B). This causes color crosstalk that changes the gradation of the display pixel (A) according to a display gradation of the display pixel (B). For example, Patent Document 1 discloses a method of solving the problem of the color crosstalk by correcting a display signal.    [Patent Document 1] Japanese Unexamined Patent Publication No. 202377/2005 (Tokukai 2005-202377 (published on Jun. 28, 2005))